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36a07dd967
* Implementation of the offsets * Fix comment * Fix spell error * Changing configure interface by addind DividersSet * Update RPI topology * Removing numDivisors from call * Removing memset clear as the constructor handles zeroed initialization * Fixing ASSERT and removing m_numDivisors * Renaming divisersSet to diviserSet --------- Co-authored-by: Simone Morettini <simone.morettini@redwirespaceeurope.com> Co-authored-by: Michael D Starch <Michael.D.Starch@jpl.nasa.gov>
56 lines
1.3 KiB
C++
56 lines
1.3 KiB
C++
/*
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* RateGroupDriverTester.cpp
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*
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* Created on: Mar 18, 2015
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* Author: tcanham
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*/
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#include <Svc/RateGroupDriver/test/ut/RateGroupDriverImplTester.hpp>
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#include <Svc/RateGroupDriver/RateGroupDriver.hpp>
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#include <Fw/Obj/SimpleObjRegistry.hpp>
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#include <gtest/gtest.h>
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#if FW_OBJECT_REGISTRATION == 1
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static Fw::SimpleObjRegistry simpleReg;
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#endif
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void connectPorts(Svc::RateGroupDriver& impl, Svc::RateGroupDriverImplTester& tester) {
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impl.set_CycleOut_OutputPort(0,tester.get_from_CycleOut(0));
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impl.set_CycleOut_OutputPort(1,tester.get_from_CycleOut(1));
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impl.set_CycleOut_OutputPort(2,tester.get_from_CycleOut(2));
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tester.connect_to_CycleIn(0,impl.get_CycleIn_InputPort(0));
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#if FW_PORT_TRACING
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// Fw::PortBase::setTrace(true);
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#endif
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// simpleReg.dump();
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}
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TEST(RateGroupDriverTest,NominalSchedule) {
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Svc::RateGroupDriver::DividerSet dividersSet{{{1, 0}, {2, 1}, {3, 0}}};
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Svc::RateGroupDriver impl("RateGroupDriver");
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impl.configure(dividersSet);
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Svc::RateGroupDriverImplTester tester(impl);
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tester.init();
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impl.init();
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// connect ports
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connectPorts(impl,tester);
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tester.runSchedNominal(dividersSet,FW_NUM_ARRAY_ELEMENTS(dividersSet.dividers));
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}
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int main(int argc, char* argv[]) {
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::testing::InitGoogleTest(&argc, argv);
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return RUN_ALL_TESTS();
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}
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