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* Removed gcov files from output folder in Svc * Removed gcov files in ActiveRateGroupComponent * removed more gcov files * Deleted more gcov files * Deleted more gcov files * Deleted more gcov files * More gcov files * Removed more gcov files * Updated Svc/ActiveLogger sdd.md file Unit Tests section * Updated Svc/ActiveRateGroup sdd.md file Unit Tests section * Updated Svc/CmdSequencer unit tests section * Updated Svc/PolyDb sdd.md file Unit Tests section * Updated Svc/RateGroupDriver sdd.md file Unit Tests section * Updated Svc/TlmChan sdd.md file Unit Tests section * Updated Svc/PrmDb sdd.md file Unit Tests section * Updated Svc/Health sdd.md file nit Test section
This component takes a primary clock tick in the system and divides it down to drive output ports. Constructor arguments define the divisors for each port. The output ports are meant to be connected to the input ports of rate groups to drive them at the correct rate. RateGroupDriverComponentAi.xml - XML definition of rate group driver component RateGroupDriverImpl.hpp(.cpp) - Implementation for rate group driver RateGroupDriverModule.mdxml - MagicDraw project file that describes rate group driver component