fprime/Autocoders/Python/schema/default/active_comp_schematron.rng
Timothy Canham d589f0a25c
VxWorks/C++ fixes (#797)
* Changed PrmBuffer m_data to m_bufferData for VxWorks

* More m_data instances

* VxWorks and virtual destructors

* Added Vxworks fatal handler compile

* Fixed active component schematron

* Changed ActiveTextLogger to use Fw::Logger to avoid VxWorks mushing of output

* fix(BufferManager): size checking logic and assert cleanup

* fix: change U64 to POINTER_CAST

Co-authored-by: Kyle Botteon <botteon@jpl.nasa.gov>
2021-07-20 16:07:42 -07:00

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XML

<?xml version="1.0" encoding="UTF-8"?>
<schema
xmlns="http://purl.oclc.org/dsdl/schematron">
<pattern id="ASYNC_PORT">
<rule context="component">
<assert test="(//component/@kind = 'active' and (count(//component/ports/port/@kind[. = 'async_input']) + count(//component/commands/command/@kind[. = 'async']) + count(//component/internal_interfaces/internal_interface) ) >= 1) or not (//component/@kind = 'active')">
Active components should have at least 1 port of kind async_input or internal_interface.
</assert>
</rule>
</pattern>
</schema>