mirror of
https://github.com/nasa/fprime.git
synced 2025-12-10 00:44:37 -06:00
15 lines
318 B
Fortran
15 lines
318 B
Fortran
module Svc {
|
|
|
|
@ A rate group driver component with input and output cycle ports
|
|
passive component RateGroupDriver {
|
|
|
|
@ Cycle input to the rate group driver
|
|
sync input port CycleIn: Cycle
|
|
|
|
@ Cycle output from the rate group driver
|
|
output port CycleOut: [RateGroupDriverRateGroupPorts] Cycle
|
|
|
|
}
|
|
|
|
}
|